This invention relates generally to semiconductor devices and fabrication thereof, and more particularly the invention relates to field effect transistors for ultra large scale integration (ULSI) semiconductor integrated circuits.
ULSI integrated Circuits having submicron channel lengths require scaling down of the geometries of devices, including the channel length of metal oxide semiconductor field effect transistors (MOSFETS or MISFETS), which is the ubiquitous workhorse in ULSI circuits. The driving force behind scaling down channel length has been an increase of packing density of devices on a typical chip which has concomitant advantages of increased functionality as well as higher throughput-yield for the process. However, the reduction of channel lengths has resulted in severe technological problems in terms of device performance and reliability.
The internal electric fields near the drain end of small geometry MOSFETS are very high, resulting in carrier heating effects and hot electron degradation of devices. To reduce the electric fields, conventionally a lightly doped N.sup.- drain (LDD) is used in MOSFETS where the doping level in the N.sup.+ drain adjacent to the channel is reduced so that the electric field near the reverse-biased N.sup.+ /P.sup.- drain-channel junction can be lowered. However, the LDD approach has severe problems for deep submicron (less than 0.5 .mu.m) channel lengths since there is an unacceptable real estate penalty for the N.sup.- regions. Further, the fields cannot be reduced sufficiently and the trapped hot electrons in the gate oxide can have serious depletion effects in the N.sup.- region. Source/drain junction depths, especially the N.sup.- junction depths, have to be made very shallow to avoid charge sharing effects such as turn-on voltage, V.sub.T, lowering with reduction of the channel length, punch-through and drain induced barrier lowering. Additionally, there are source/drain series resistance problems associated with the shallow N.sup.- region, and to a lesser degree with the shallow N.sup.+ regions. Also, there can be enhanced leakage in the N.sup.- region due to band-to-band tunneling or gate induced drain leakage (GIDL). Further, there is a N.sup.- source/drain and gate overlap Miller capacitance and a large source/drain junction capacitance because of the high tank doping required for punch-through protection. All of these factors pose severe technological challenges in fabricating the devices, slow down circuit switching speeds, and increase active power dissipation.
The present invention is directed to an improved MOSFET device for ULSI circuits and the manufacture thereof.